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1 mbit (128k x 8) nvsr am with real-time clock preliminary cy14b101k cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06401 rev. *e revised march 01, 2007 features ? data integrity of cypress nvsram combined with full featured real-time clock (rtc) ? watchdog timer ? clock alarm with programmable interrupts ? capacitor or battery backup for rtc ? 25 ns, 35 ns, and 45 ns access times ? ?hands-off? automatic store on power down with only a small capacitor ? store to quantumtrap? initiated by software, device pin, or on power down ? recall to sram initiated by software or on power up ?infinite read, write, and recall cycles ? high reliability ? endurance to 200,000 cycles ? data retention: 20 years @55 c ? 10 ma typical i cc at 200 ns cycle time ? single 3v operation +20%, ?10% ? commercial and industrial temperature ? ssop package (rohs compliant) functional description the cypress cy14b101k combines a 1 mbit nonvolatile static ram with a full featured real -time clock in a monolithic integrated circuit. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolatile memory. the sram can be read and written an infinite number of times, while independent, nonvolatile data resides in the nonvolatile elements. the real-time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. the alarm function is programmable for one time alarm or periodic seconds, minut es, hours, or days. there is also a programmable watchdog timer for process control. logic block diagram store/ recall control power control software detect static ram array 1024 x 1024 quantumtrap 1024 x 1024 store recall column io column dec row decoder input buffers oe ce we hsb v cc v cap a 15 - a 0 a 0 a 1 a 2 a 3 a 4 a 10 a 11 a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 a 15 a 16 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 rtc mux a 16 - a 0 x 1 x 2 int v rtcbat v rtccap [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 2 of 24 pin configurations pin definitions pin name io type description a 0 ? a 16 input address inputs used to select one of the 131,072 bytes of the nvsram . dq0 ? dq7 input output bidirectional data io lines. used as input or output lines depending on operation nc no connect no connects . this pin is not connected to the die we input write enable input, active low . when selected low, enables data on the io pins to be written to the address location latched by the falling edge of ce . ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the io pins to tri-state. x 1 output crystal connection , drives crystal on start up. x 2 input crystal connection for 32.768 khz crystal. v rtccap power supply capacitor supplied backup rtc supply voltage . (left unconnected if v rtcbat is used) v rtcbat power supply battery supplied backup rtc supply voltage . (left unconnected if v rtccap is used) int output interrupt output . program to respond to the clock alarm, the watchdog timer and the power monitor. programmable to either active high (push/pull) or low (open drain). v ss ground ground for the device . must be connected to ground of the system. v cc power supply power supply inputs to the device . hsb input output hardware store busy . when low this output indicates a hardware store is in progress. when pulled low external to the chip it initiates a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). v cap power supply autostore tm capacitor. supplies power to nvsram during power loss to store data from sram to nonvolatile elements. v cap a 16 a 14 a 12 a 7 a 6 a 5 a 4 v cc a 15 hsb we a 13 a 8 a 9 a 11 oe a 10 dq dq7 6 dq5 ce dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 int nc nc nc v ss nc dq0 a 3 a 2 a 1 a 0 dq1 dq2 nc nc nc nc v ss nc v cc 48-ssop top view (not to scale) v rtcbat x 1 x 2 v rtccap [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 3 of 24 device operation the cy14b101k nvsram is made up of two functional components paired in the same physical cell, a sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. transfer of the data can be from the sram to the nonvolatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). this unique architecture allows all cells to be stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the cy14b101k supports infinite reads and writes just like a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 200,000 store operations. sram read the cy14b101k performs a read cycle whenever ce and oe are low, while we and hsb are high. the address specified on pins a 0-16 determines which of the 131,072 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs will be valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly responds to address changes within the t aa access time without the need for transitions on any control input pins. it remains valid until another address change, or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must remain stable until either ce or we goes high, at the end of the cycle. the data on the common io pins dq 0?7 will be written into the memory if the data is valid t sd before the end of a we -controlled write or before the end of an ce -controlled write. it is recommended that oe be kept high during the entire write cycle to avoid data bus contention on common io lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b101k stores data to nvsram using one of three storage operations. these three operations are hardware store activated by hsb , software store activated by an address sequence, and autostore on device power down. autostore operation is a unique feature of quantumtrap technology and is enabled by default on the cy14b101k. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation will be initiated with power provided by the v cap capacitor. figure 1 shows the proper connection of the storage capacitor (v cap ) for automatic store op eration. refer to the table , ?dc electrical characteristics,? on page 14 for the size of v cap . the voltage on the v cap pin is driven to 5v by a charge pump internal to the chip. a pull up must be placed on we to hold it inactive during power up. to reduce unnecessary nonvolatile stores, autostore and hardware store operations will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. soft ware initiated store cycles are performed regardless of whether a write operation has taken place. monitor the hsb signal by the syst em to detect if an autostore cycle is in progress. hardware store (hsb ) operation the cy14b101k provides the hsb pin for controlling and acknowledging the store operations. use the hsb pin to request a hardware store cycle. when the hsb pin is driven low, the cy14b101k conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram took place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store opera tion is initiated. after hsb goes low, the cy14b101k cont inues sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it will be allowed a time, t delay , to complete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. during any store operation, regardless of how it was initiated, the cy14b101k c ontinues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store oper ation the cy14b101k remains disabled until the hsb pin returns high. leave the hsb unconnected if it is not used. figure 1. autostore mode v cc v cc v cap v cap we 10k ohm 0.1 f u [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 4 of 24 hardware recall (power up) during power up, or after any low power condition (v cc cy14b101k preliminary document #: 001-06401 rev. *e page 5 of 24 table 1. mode selection ce we oe a15 ? a0 mode io power h x x x not selected output high-z standby l h l x read sram output data active l l x x write sram input data active l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active [1, 2, 3] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [1, 2, 3] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high-z active i cc2 [1, 2, 3] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high-z active [1, 2, 3] notes 1. the six consecutive addr ess locations must be in the order listed. we must be high during all six cycles to enable a nonvolatile cycle. 2. while there are 17 address lines on the cy14b101k, only the lower 16 lines are used to control software modes. 3. io state depends on the state of oe . the io table shown is based on oe low. [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 6 of 24 low average active power cmos technology provides the cy14b101k, the benefit of drawing significa ntly less current when it is cycled at times longer than 50 ns. figure 2 on page 6 shows the relationship between i cc and read/write cycle time. worst case current consumption is sreadhown for commercial temperature range, v cc = 3.6v, and chip enable at maximum frequency. only standby current is drawn when the chip is disabled. the overall average current drawn by the cy14b101k depends on the following items: 1. the duty cycle of chip enable. 2. the overall cycle rate for accesses. 3. the ratio of reads to writes. 4. the operating temperature. 5. the v cc level. 6. io loading. real-time clock operation nvtime operation the cy14b101k offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. internal double buffering of the clock and the clock/timer information registers prevents accessing transitional internal clock data during a read or write operation. double buffering also circumvents disrupting normal timing counts or clock accuracy of the internal clock while accessing clock data. clock and alarm registers store data in bcd format. clock operations the clock registers maintain ti me up to 9,999 years in one second increments. the user can set the time to any calendar time and the clock automatically keeps track of days of the week, month, leap years, and century transitions. there are eight registers dedicated to the clock functions that are used to set time with a write cycle and to read time during a read cycle. these registers cont ain the time of day in bcd format. bits defined as ?0? are currently not used and are reserved for future use by cypress. reading the clock while the double-buffered rtc register structure reduces the chance of reading incorrect dat a from the clock, you have to halt internal updates to the cy14b101k clock registers before reading clock data to prevent the reading of data in transition. stopping the internal register updates does not affect clock accuracy. the update process is stopped by writing a ?1? to the read bit ?r? (in the flags regi ster at 0x1fff0), and will not restart until a ?0? is written to the read bit. the rtc registers can then be read while the internal clock continues to run. within 20 ms after a ?0? is written to the read bit, all cy14b101k registers are simultaneously updated. setting the clock setting the write bit ?w? (in the flags register at 0x1fff0) to a ?1? halts updates to the cy14b101k registers. the correct day, date, and time can then be written into the registers in 24-hour bcd format. the time written is referred to as the ?base time.? this value is stor ed in nonvolatile registers and used in calculation of the current time. resetting the write bit to ?0? transfers those values to the actual clock counters, after which the clock resumes normal operation. backup power the rtc in the cy14b101k is intended for permanently powered operation. either the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chosen for the application. when primary power, v cc , fails and drops below v switch the device will switch to the backup power supply. the clock oscillator uses very little current which maximizes the backup time available from the backup source. regardless of clock operation with the primary source removed, the data stored in nvsram is secure, having been stored in the nonvolatile elements as power was lost. during backup operation the cy14b101k consumes a maximum of 300 na at 2 volts. capacitor or battery values must be chosen according to the application. backup time values based on maximum current specs are shown in the following table. nominal times are approximately three times longer. using a capacitor has the obvious advantage of recharging the backup source each time t he system is powered up. if a battery is used, a 3v lithium is recommended and the cy14b101k will only source current from the battery when the primary power is removed. the battery will not however be figure 2. current vs. cycle time table 2. rtc backup time capacitor value backup time 0.1f 72 hours 0.47f 14 days 1.0f 30 days [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 7 of 24 recharged at any time by the cy14b101k. the battery capacity should be chosen for total anticipated cumulative downtime required over th e life of the system. stopping and starting the oscillator the oscen bit in the calibration regi ster at 0x1fff8 controls the starting and stopping of the oscillator. this bit is nonvolatile and shipped to customers in the ?enabled? (set to 0) state. to preserve battery life while system is in storage, oscen should be set to a 1. this turns off the oscillator circuit extending the battery life. if the oscen bit goes from disabled to enabled, it takes approximately 5 seconds (10 seconds max) for the oscillator to start. the cy14b101k has the ability to detect oscillator failure. this is recorded in the oscf (oscillator failed bit) of the flags register at address 0x1fff0. when the device is powered on (v cc goes above v switch ) the oscen bit is checked for ?enabled? status. if the oscen bit is enabled and the oscillator is not active, the oscf bit is set. the user should check for this condition and then write a 0 to clear the flag. it should be noted that in addition to setting the oscf flag bit, the time registers are reset to the ?b ase time? (see the section setting the clock on page 6 ), which is the value last written to the timekeeping registers. the c ontrol/calibration register and the oscen bit are not affected by the oscillator failed condition. if the voltage on the backup supply (either v rtccap or v rtcbat ) falls below their minimum level, the oscillator may fail, leading to the oscillator failed condition, which can be detected when system power is restored. the value of oscf should be reset to 0 when the time registers are written for the first time. this initializes the state of this bit which may have be come set when the system was first powered on. calibrating the clock the rtc is driven by a quartz -controlled oscillator with a nominal frequency of 32.768 khz. clock accuracy depends on the quality of the crystal, usually specified to 35 ppm limits at 25c. this error could equate to +1.53 minutes in accordance with month. the cy14b 101k employs a calibration circuit that can improve the accuracy to +1/?2 ppm at 25c. the calibration circuit adds or subtracts counts from the oscillator divider circuit. the number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in calibration register at 0x1fff8. adding counts speeds the clock up; subtracting counts slows the clock down. the calibration bits occupy the five lower order bits in the control register 8. set these bits to represent any value between 0 and 31 in binary form. bit d5 is a sign bit, where a ?1? indicates positive calibration and a ?0? indicates negative calibration. calibration occurs within a 64 minu te cycle. the first 62 minutes in the cycle ma y, once in accordance with minute, have one second eith er shortened by 128 or lengthened by 256 oscillator cycles. if a binary ?1? is loaded into the register, only the first two minutes of the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affect ed, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829,120 actual o scillator cycles. that is 4.068 or ?2.034 ppm of adjustment in accordance with calibration step in the calibration register. in order to determine how to set the calibration one may set the cal bit in the flags register at 0x1fff0 to 1, which causes the int pin to toggle at a nominal 512 hz. any deviation measured from the 512 hz indicates the degree and direction of the required correction. for example, a reading of 512.010124 hz would indicate a +20 ppm error, requiring a ?10 (001010) to be loaded into the calibration register. note that setting or changing the cali bration register does not affect the frequency test output frequency. alarm the alarm function compares user programmed values to the corresponding time-of-day values. when a match occurs, the alarm event occurs. the alarm drives an internal flag, af, and may drive the int pin if desired. there are four alarm match fi elds. they are date, hours, minutes, and seconds. each of these fields also has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field will be used in the match process. depending on the match bits, the alarm can occur as specifically as one particular second on one day of the month, or as frequently as once in accordance with second continuously. the msb of each alarm register is a match bit. selecting none of the match bits (all 1s) indicates that no match is required. the alarm occurs every second. setting the match select bit for seconds to ?0? causes the logic to match the seconds alarm value to the current time of day. since a match occurs for only one value in accordance with minute, the alarm occurs once in accordance with minute. likewise, setting the seconds and minutes match bits causes an exact match of these values. thus, an alarm occurs once in accordance with hour. setting seconds, minutes, and hours causes a match once in accordance with day. lastly, selecting all match values causes an exact time and date match. selecting other bit combinations will not produce meaningful results; however the alarm circuit should follow the functions described. there are two ways a user can detect an alarm event, by reading the af flag or monitoring the int pin. the af flag in the flags register at 0x1fff0 will indicate that a date and time match has occurred. the af bit will be set to 1 when a match occurs. reading the flags/contro l register clears the alarm flag bit (and all others). a hardware interrupt pin may also be used to detect an alarm event. watchdog timer the watchdog timer is a free running down counter that uses the 32-hz clock (31.25 ms) derive d from the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register. the counter consists of a loada ble register and a free-running counter. on power up, the watchdog timeout value in register 0x1fff7 is loaded into the counter load register. counting begins on power up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to 1. the counter is [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 8 of 24 compared to the terminal value of 0. if the counter reaches this value, it causes an internal flag and an optional interrupt output. you can prevent the time out interrupt by setting wds bit to 1 before the counter reachi ng 0. this causes the counter to be reloaded with the watchdog timeout value and to be restarted. as long as the user sets the wds bit before the counter reaching the terminal value, the interrupt and flag never occurs. write new timeout values by setting the watchdog write bit to 0. when the wdw is 0 (from the previous operation), new writes to the watchdog timeout value bits d5?d0 allow the timeout value to be modified. when wdw is a 1, writes to bits d5 ? d0 will be ignored. the wdw function allows a user to set the wds bit without concern that the watchdog timer value will be modified. a logical diagram of the watchdog timer is shown in figure 3 . note that setting the watchdog timeout value to 0 would be otherwise meaningless and therefore disables the watchdog function. the output of the watchdog timer is a flag bit wdf that is set if the watchdog is allowed to timeout. the flag is set upon a watchdog timeout and cleared when the flags/control register is readread by the user. the user can also enable an optional interrupt source to drive the int pin if the watchdog timeout occurs. power monitor the cy14b101k provides a power management scheme with power fail interrupt capability. it also controls the internal switch to backup power for the clock and protects the memory from low v cc access. the power monitor is based on an internal band gap reference circuit that compares the v cc voltage to various thresholds. as described in the autostore section previously, when v switch is reached as v cc decays from power loss, a data store operation is initiated from sram to the nonvolatile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source no data may be read or written and the clock functions are not available to the user. the clock continues to operate in the background. updated clock data is available to the user after vcc has been restored to the device and threcall delay (see autostore/power up recall on page 16 ) . interrupts the cy14b101k provides three potential interrupt sources. they include the watchdog timer, the power monitor, and the clock/calendar alarm. individually enable each and assign to drive the int pin. in addition, each has an associated flag bit that the host processor can us e to determine the cause of the interrupt. some of the sources ha ve additional control bits that determine functional behavior. in addition, the pin driver has three bits that specify its behavior when an interrupt occurs. the three interrupts each have a source and an enable. both the source and the enable must be active (true high) in order to generate an interrupt output. only one source is necessary to drive the pin. the user can identify the source by reading the flags/control register, which contains the flags associated with each source. all flags are cleared to 0 when the register is read. the flags will be cleared only after a complete read cycle (we high); the power mo nitor has two programmable settings that are explained in the power monitor section. once an interrupt source is active, the pin driver determines the behavior of the output. it has two programmable settings as shown in the following section. pin driver control bits are located in the interrupts register. according to the programming selections, the pin can be driven in the backup mode for an alarm interrupt. in addition, the pin can be an active low (open drain) or an active high (push pull) driver. if programmed for operation during backup mode, it can only be active low. lastly, the pin can provide a one shot function so that the ac tive condition is a pulse or a level condition. in one shot mode, the pulse width is internally fixed at approximately 200 ms. this mode is intended to reset a host microcontroller. in level mode, the pin goes to its active polarity until the flags/control register is read by the user. this mode is intended to be used as an interrupt to a host microcontroller. the interrupt regi ster is initialized to 00h. the control bits are summarized as follows: watchdog interrupt enable ? wie . when set to 1, the watchdog timer drives the int pin as well as an internal flag when a watchdog timeout occurs . when wie is set to 0, the watchdog timer affects on ly the internal flag. alarm interrupt enable ? aie . when set to 1, the alarm match drives the int pin as well as an internal flag. when set to 0, the alarm match only affects to internal flag. power fail interrupt enable ? pfe . when set to 1, the power fail monitor drives the pin as well as an internal flag. when set to 0, the power fail monitor affects only the internal flag. high/low ? h/l . when set to a 1, the int pin is active high and the driver mode is push-pull. the int pin can drive high only when v cc > v switch . when set to a 0, the int pin is active low and the drive mode is open drain. active low (open drain) is operational even in battery backup mode. pulse/level ? p/l . when set to a 1 and an interrupt occurs, the int pin is driven for approximately 200 ms. when p/l is set to a 0, the int pin is driven high or low (determined by h/l) until the flags/control register is readd. when an enabled interrupt source activates the int pin, an external host can read the flags/control register to determine the cause. remember that all flags will be cleared figure 3. watchdog timer block diagram 1 hz oscillator clock divider counter zero compare wdf wds load register wdw d q q watchdog register write to watchdog register 32 hz 32,768 khz [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 9 of 24 when the register is read. if the int pin is programmed for level mode, then the condition clears and the int pin returns to its inactive state. if the pin is programmed for pulse mode, then reading the flag also clears the flag and the pin. the pulse will not complete its specified duration if the flags/control register is read. if the int pin is used as a host reset, then the flags/control register should not be read during a reset. during a power on reset with no battery, the interrupt register is automatically loaded with th e value 24h. this causes power fail interrupt to be enabled with an active low pulse. flags register ? the flags register has three flag bits: wdf, af, and pf. these flag bits are initialized to 00h. these flags are set by the watchdog timeout, alarm match, or power fail monitor respectively. the processor can either poll this register or enable interrupts to be informed when a flag is set. the flags are automatically reset once the register is read. rtc recommended component configuration figure 4. interrupt block diagram recommended values y1 = 32.768 khz rf = 10 m ? c 1 = 0 c 2 = 56 pf wdf - watchdog timer flag wie - watchdog interrupt pf - power f ail flag pfe - power fail enable af - alarm flag aie - alarm interrupt enable p/l - pulse level h/l - high/low watchdog timer power monitor clock alarm vint wdf wie pf pfe af aie p/l pin driver h/l int v cc v ss enable [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 10 of 24 table 3. rtc register map register bcd format data function/range d7 d6 d5 d4 d3 d2 d1 d0 0x1ffff 10s years years years: 00 ? 99 0x1fffe 0 0 0 10s months months months: 01 ? 12 0x1fffd 0 0 10s day of month day of month day of month: 01 ? 31 0x1fffc 0 0 0 0 0 day of week day of week: 01 ? 07 0x1fffb 0 0 10s hours hours hours: 00 ? 23 0x1fffa 0 10s minutes minutes minutes: 00 ? 59 0x1fff9 10s seconds seconds seconds: 00 ? 59 0x1fff8 oscen 0 cal sign calibration calibration values [4] 0x1fff7 wds wdw wdt watchdog [4] 0x1fff6 wie aie pfe 0 h/l p/l 0 0 interrupts [4] 0x1fff5 m 0 10s alarm date alarm day alarm, day of month: 01 ? 31 0x1fff4 m 0 10s alarm hours alarm hours alarm, hours: 00 ? 23 0x1fff3 m 10 alarm minutes alarm minutes alarm, minutes: 00 ? 59 0x1fff2 m 10 alarm minutes alarm, seco nds alarm, seconds: 00 ? 59 0x1fff1 10s centuries centuries centuries: 00 ? 99 0x1fff0 wdf af pf oscf 0 cal w r flags [4] table 4. register map detail 0x1ffff time keeping ? years d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of the year. lower nibb le contains the value for years; upper nibble contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0 ? 99. 0x1fffe time keeping ? months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. the range for the register is 1 ? 12. 0x1fffd time keeping ? date d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the date of the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. the range for the register is 1 ? 31. leap years are automatically adjusted for. 0x1fffc time keeping ? day d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble contains a value that correlates to day of the week. day of the week is a ri ng counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, as the day is not integrated with the date. note 4. this register contains a binary, not bcd, value. . [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 11 of 24 0x1fffb time keeping ? hours d7 d6 d5 d4 d3 d2 d1 d0 12/24 0 10s hours hours contains the bcd value of hours in 24 hour format. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operat es from 0 to 2. the range for the register is 0 ? 23. 0x1fffa time keeping ? minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. the range for the register is 0 ? 59. 0x1fff9 time keeping ? seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. the range for the register is 0 ? 59. 0x1fff8 calibration/control d7 d6 d5 d4 d3 d2 d1 d0 oscen 0 calibration sign calibration oscen oscillator enable. when set to 1, the o scillator is halted. when set to 0, the o scillator runs. disabling the oscillator saves battery/capacitor power during storage. on a no batter y power up, this bit is set to 0. calibration sign determines if the calibration adjustm ent is applied as an addition to or as a subtraction from the time base. calibration these five bits control the calibration of the clock. 0x1fff7 watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to 1 reloads and restarts the watchdog timer. setting the bit to 0 has no affect. the bit is cleared automatically once the watchdog timer is reset. the wds bit is write only. reading it always returns a 0. wdw watchdog write enable. setting this bit to 1 masks t he watchdog timeout value (wdt5?wdt0) so it cannot be written. this allows the user to strobe the watchdog without disturbing the timeout value. setting this bit to 0 allows bits 5 ? 0 to be written on the next write to the watchd og register. the new value will be loaded on the next internal watchdog clock after the write cycle is complete. this function is explained in more detail in the watchdog timer section. wdt watchdog timeout selection. the watchdog timer interval is selected by the 6-bit value in this register. it represents a multiplier of the 32 hz c ount (31.25 ms). the minimum range or timeout value is 31.25 ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3 fh). setting th e watchdog timer register to 0 disables the timer. these bits can be written only if the wdw bit was cleared to 0 on a previous cycle. table 4. register map detail (continued) [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 12 of 24 0x1fff6 interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfie 0 h/l p/l 00 wie watchdog interrupt enable. when set to 1 and a watchd og timeout occurs, the watchdog timer drives the int pin as well as the wdf flag. when set to 0, the watchdog timeout affects only the wdf flag. aie alarm interrupt enable. when set to 1, the alarm match driv es the int pin as well as the af flag. when set to 0, the alarm match only affects the af flag. pfie power fail enable. when set to 1, the alarm match drives the int pin as well as the af flag. when set to 0, the power fail monitor affects only the pf flag. 0 reserved for future use. h/l high/low. when set to a 1, the int pin is driven active high. when set to 0, the int pin is open drain, active low. p/l pulse/level. when set to a 1, the int pin is driven active (determined by h/l) by an inte rrupt source for approximately 200 ms. when set to a 0, the int pin is driven to an active leve l (as set by h/l) until the flags/control register is read. 0x1fff5 alarm ? day d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the month and the mask bit to se lect or deselect the date value. m match. setting this bit to 0 causes the date value to be us ed in the alarm match. setting this bit to 1 causes the match circuit to ignore the date value. 0x1fff4 alarm ? hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the ma sk bit to select or deselect the hours value. m match. setting this bit to 0 causes the hours value to be used in the alarm match. setting this bit to 1 causes the match circuit to ignore the hour value. 0x1fff3 alarm ? minutes d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm minutes alarm minutes contains the alarm value for the minutes and the ma sk bit to select or deselect the minutes value. m match. setting this bit to 0 causes the minutes value to be used in the alarm match. setting this bit to 1 causes the match circuit to ignore the minute value. 0x1fff2 alarm ? seconds d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm seconds alarm seconds contains the alarm value for the seconds and the ma sk bit to select or dese lect the second value. m match. setting this bit to 0 causes the second value to be us ed in the alarm match. setting this bit to 1 causes the match circuit to ignore the second value. 0x1fff1 time keeping ? centuries d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s centuries centuries table 4. register map detail (continued) [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 13 of 24 0x1fff0 flags d7 d6 d5 d4 d3 d2 d1 d0 wdfaf pfoscf0calw r wdf watchdog timer flag. this read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. it is cleared to 0 when the flags/control register is read. af alarm flag. this read only bit is set to 1 when the ti me and date match the values stored in the alarm registers with the match bits = 0. it is cleared when the flags/control register is read. pf power fail flag. this read only bit is set to 1 when power falls below the power fail threshold v switch . it is cleared to 0 when the flags/control register is read. oscf oscillator fail flag. set to 1 on power up only if the oscill ator is not running in the firs t 5 ms of power on operation. this indicates that time counts are no longer valid. the user must reset this bit to 0 to clear this condition. the chip will not clear this flag. this bit survives power cycles. cal calibration mode. when set to 1, a 512 hz square wave is output on the int pin. when set to 0, the int pin resumes normal operation. this bit defaults to 0 (disabled) on power up. w write time. setting the w bit to 1 freeze updates of th e timekeeping registers. the us er can then write them with updated values. setting the w bit to 0 causes the contents of the time registers to be transferred to the timekeeping counters. the w-bit enables writes to rtc, alar m, calibration, interrupt, and flag registers. r read time. setting the r bit to 1 copies a static image of the timekeeping registers and places them in a holding register. the user can then read them without concerns over changing values causing system errors. the r bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 before reading again. table 4. register map detail (continued) [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 14 of 24 maximum ratings exceeding maximum ratings may impair the useful life of device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc relative to gnd .. ....... ?0.5v to 4.1v voltage applied to outputs in high-z state .......................................?0.5v to v cc + 0.5v input voltage .......................................... ?0.5v to vcc + 0.5v transient voltage (<20 ns) on any pin to ground potential ..................?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount pb soldering temperature (3 seconds).......................................... +260 c output short circuit current [5] .................................... 15 ma static discharge voltage.......................................... > 2001v (in accordance with mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial ?40 c to +85 c 2.7v to 3.6v dc electrical characteristics over the operating range (vcc = 2.7v to 3.6v) [6, 7, 8] parameter description test conditions min max unit i cc1 average v cc current t rc = 25 ns t rc = 35 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. commer cial 65 55 50 ma ma ma industrial 55 (t rc = 45 ns) ma ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store 6ma i cc3 average v cc current at t avav = 200 ns, 3v, 25c typical we > (v cc ? 0.2). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. 10 ma i cc4 average v cap current during autostore cycle all inputs do not care, v cc = max average current for duration t store 3ma i sb v cc standby current we > (v cc ? 0.2). all others v in < 0.2v or >(v cc ?0.2v). standby current level after nonvol- atile cycle is complete. inputs are static. f = 0 mhz 3ma i ix input leakage current v cc = max, v ss < v in < v cc ?1 +1 a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih ?1 +1 a v ih input high voltage [9] 2.0 v cc + 0.3 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap storage capacitor between v cap pin and v ss , 5v rated 17 120 f notes 5. outputs shorted for no more than one second. no more than one output shorted at a time. 6. typical conditions for the active current shown at the beginning of the data sheet are average values at 25c (room temperatu re), and v cc = 3v. not 100% tested. 7. the hsb pin has i out = ?10 a for v oh of 2.4 v, this parameter is characterized but not tested. 8. the int pin is open drain and does not source or sink current when interrupt register bit d3 is low. 9. v ih changes by 100 mv when v cc > 3.5v. [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 15 of 24 capacitance [10] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0 v 7pf c out output capacitance 7 pf thermal resistance [10] parameter description test conditions 48-ssop unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. tbd c/w jc thermal resistance (junction to case) tbd c/w ac test loads ac test conditions 3.0v output 5 pf r1 577 ? r2 789 ? 3.0v output 30 pf r1 577 ? r2 789 ? for tri-state specs input pulse levels ..................................................0 v to 3 v input rise and fall times (10% - 90%)........................ < 5 ns input and output timing referenc e levels ......... .......... 1.5 v note 10. these parameters are guaranteed but not tested. [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 16 of 24 ac switching characteristics parameter description 25 ns part 35 ns part 45 ns part unit min max min max min max cypress parameter alt. parameter sram read cycle t ace t acs chip enable access time 25 35 45 ns t rc [11] t rc read cycle time 25 35 45 ns t aa [12] t aa address access time 25 35 45 ns t doe t oe output enable to data valid 12 15 20 ns t oha [12] t oh output hold after address change 3 3 3 ns t lzce [13] t lz chip enable to output active 3 3 3 ns t hzce [13] t hz chip disable to output inactive 10 13 15 ns t lzoe [13] t olz output enable to output active 0 0 0 ns t hzoe [13] t ohz output disable to output inactive 10 13 15 ns t pu [10] t pa chip enable to power active 0 0 0 ns t pd [10] t ps chip disable to power standby 25 35 45 ns sram write cycle t wc t wc write cycle time 25 35 45 ns t pwe t wp write pulse width 20 25 30 ns t sce t cw chip enable to end of write 20 25 30 ns t sd t dw data setup to end of write 10 12 15 ns t hd t dh data hold after end of write 0 0 0 ns t aw t aw address setup to end of write 20 25 30 ns t sa t as address setup to start of write 0 0 0 ns t ha t wr address hold after end of write 0 0 0 ns t hzwe [13, 14] t wz write enable to output disable 10 13 15 ns t lzwe [13] t ow output active after end of write 3 3 3 ns autostore/power up recall parameter description cy14b101k unit min max t hrecall [15] power up recall duration 20 ms t store [16, 17] store cycle duration 12.5 ms v switch low voltage trigger level 2.65 v t vccrise vcc rise time 150 s notes 11. we must be high during sram read cycles. 12. device is continuously selected with ce and oe both low. 13. measured 200 mv from steady state output voltage. 14. if we is low when ce goes low, the outputs remain in the high impedance state. 15. t hrecall starts from the time v cc rises above v switch . 16. if an sram write has not taken place since the last nonvolatile cycle, no store takes place. 17. industrial grade devices require 15 ms max. [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 17 of 24 software controlled store/recall cycle [18, 19, 20] parameter description 25 ns part 35 ns part 45 ns part unit min max min max min max t rc store/recall initiation cycle time 25 35 45 ns t as address setup time 0 0 0 ns t cw clock pulse width 20 25 30 ns t ghax address hold time 1 1 1 ns t recall recall duration 100 100 100 s t ss [21, 22] soft sequence processing time 70 70 70 s hardware store cycle parameter description cy14b101k unit min max t delay [23] time allowed to complete sram cycle 1 70 s t hlhx hardware store pulse width 15 ns rtc characteristics parameters description tes t conditions min max units i bak [24] rtc backup current commercial 300 na industrial 350 na v rtcbat [25] rtc battery pin voltage commercial 1.8 3.3 v industrial 1.8 3.3 v v rtccap [26] rtc capacitor pin voltage commercial 1.2 2.7 v industrial 1.2 2.7 v tocs rtc oscillator time to start @min temperature from power up or enable commercial 10 sec @25 c temperature from power up or enable commercial 5 sec @min temperature from power up or enable industrial 10 sec @25 c temperature from power up or enable industrial 5 sec notes 18. the software sequence is clocked with ce controlled or oe controlled reads. 19. the six consecutive addres ses must be read in the order listed in the mode selection table. we must be high during a ll six consecutive cycles. 20. a 600 ? resistor must be connected to hsb to use the software command. 21. this is the amount of time it takes to take action on a soft sequence command. vcc power must re main high to effectively reg ister the command. 22. commands like store and recall lock out io until operation is complete which further increases this time. see the specific c ommand. 23. read and write cycles in progress before hsb are given this amount of time to complete. 24. from either v rtccap or v rtcbat. 25. typical = 3.0v during normal operation. 26. typical = 2.4v during normal operation. [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 18 of 24 switching waveforms sram read cycle 1 (address controlled) [11, 12, 27] sram read cycle 2 (ce and oe controlled) [11, 27] t rc t aa t oha address dq (data out) data valid address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe t hzoe data valid active standby t pu dq (data out) icc note 27. hsb must remain high during read and write cycles. [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 19 of 24 sram write cycle 1 (we controlled) [27, 28] sram write cycle 2 (ce controlled) switching waveforms (continued) t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid note 28. ce or we must be > v ih during address transitions. [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 20 of 24 figure 5. autostor e/power up recall figure 6. ce -controlled software store/recall cycle [19] switching waveforms (continued) v cc v switch t store t store t hrecall t hrecall autostore power-up recall read & write inhibited store occurs only if a sram write has happened no store occurs without atleast one sram write t vccrise a a t rc t rc t sa t sce t glax t store / t recall data valid data valid address # 1 address # 6 high impedance address ce oe dq (data) a a a a a a a a a a a a t ghax [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 21 of 24 figure 7. oe -controlled software store/recall cycle [19] figure 8. hardware store cycle figure 9. soft sequence processing [21, 22] switching waveforms (continued) t rc t rc address # 1 address # 6 address t sa t sce t glax t store / t recall data valid data valid high impedance ce oe dq (data) a a a a a a a a a a a a a a t ghax t hlhx t store t hlbl t delay data valid data valid high impedance high impedance hsb (in) dq (data out) hsb (out) a a a a a a a a a a address # 1 address # 6 address # 1 address # 6 soft sequence command t ss 34 soft sequence command t ss 34 address v cc [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 22 of 24 ordering information all of the above mentioned parts are of ?pb-free? type. shaded areas contain advance information. contact your local cypress sales representative for availability of these parts. speed (ns) ordering code package diagram package type operating range 25 cy14b101k-sp25xct 51-85061 48-pin ssop commercial 35 cy14b101k-sp35xct 51-85061 48-pin ssop commercial 45 cy14b101k-sp45xct 51-85061 48-pin ssop commercial 45 CY14B101K-SP45XIT 51-85061 48-pin ssop industrial cy14b101k-sp45xi 51-85061 48-pin ssop option: t - tape & reel blank - std. speed: 25 - 25 ns 45 - 45 ns data bus: k - x8 + rtc density: 101 - 1 mb voltage: b - 3.0v cypress part numbering nomenclature cy 14 b 101 k - sp 25 x c t nvsram 14 - autostore + software store + hardware store package: sp - 48 ssop 35 - 35 ns temperature: c - commercial (0 to 70c) i - industrial (?40 to 85c) pb-free [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 23 of 24 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems wh ere a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram figure 10. 48-pin shrunk small outline package, 51-85061 autostore and quantumtrap are registered trademarks of simtek cor poration. all products and company names mentioned in this document are the trademarks of their respective holders. 51-85061-*c [+] feedback [+] feedback
cy14b101k preliminary document #: 001-06401 rev. *e page 24 of 24 document history page document title: cy14b101k 1 mbit (128k x 8) nvsram with real-time clock document number: 001-06401 rev. ecn no. issue date orig. of change description of change ** 425138 see ecn tup new data sheet *a 437321 see ecn tup show data sheet on external web *b 471966 see ecn tup changed i cc3 from 5 ma to 10 ma changed isb from 2 ma to 3 ma changed v ih(min) from 2.2v to 2.0v changed t recall from 40 s to 100 s changed endurance from 1million cycles to 500k cycles changed data retention from 100 years to 20 years added soft sequence processing time waveform updated part numbering nomenclature and ordering information added rtc characteristics table added rtc recommended component configuration *c 503272 see ecn pci changed from advance to preliminary changed the term ?unlimited? to ?infinite? changed endurance from 500k cycles to 200k cycles added temperature spec. to data retention - 20 years at 55 c removed icc 1 values from the dc table for 25 ns and 35 ns industrial grade changed icc 2 value from 3 ma to 6 ma in the dc table added a footnote on v ih added footnote 18 related to using the software command changed v switch(min) from 2.55v to 2.45v updated part nomenclature table and ordering information table *d 597002 see ecn tup removed v switch(min) spec from the autostore/power up recall table changed t glax spec from 20 ns to 1 ns added t delay(max) spec of 70 s in the hardware store cycle table removed t hlbl specification changed t ss specification form 70 s (min) to 70 s (max) changed v cap(max) from 57 f to 120 f *e 688776 see ecn vkn added footnote 7 related to hsb added footnote 8 related to int pin changed t glax to t ghax removed abe bit from interrupt register [+] feedback [+] feedback

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